1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device applicable to a peripheral circuit of a DRAM (Dynamic Random Access Memory), and a method of manufacturing thereof.
2. Description of the Background Art
In recent years, the demand for semiconductor memory devices are rapidly increasing due to the remarkable spread of information equipment of computers. Semiconductor memory devices having large functional storage capacity and capable of high speed operation are required. Accordingly, developments in techniques are carried out regarding high density integration, quick response, and high reliability of semiconductor memory devices.
A DRAM in semiconductor memory devices is known as being capable of random input/output of storage information. A DRAM usually comprises a memory cell array which is the storage region for storing a plurality of storage information, and a peripheral circuit required for input from and output to an external source. FIG. 3 is a block diagram showing a general DRAM structure. Referring to FIG. 3, a DRAM 50 comprises a memory cell array 51 for storing data signal of storage information, a row-and-column address buffer 52 for receiving external address signals to select memory cells forming a unit storage circuit, a row decoder 53 and a column decoder 54 for specifying a memory cell by decoding the address signal, a sense refresh amplifier 55 for amplifying and reading out the signal stored in the specified memory cell, a data-in buffer 56 and a data-out buffer 57 for data input/output, and a clock generator 58 for generating a clock signal.
The memory cell array 51 occupying a large area on the semiconductor chip has a plurality of memory cells for storing unit storage information arranged in a matrix manner. A memory cell is generally implemented with one MOS transistor and one capacitor connected thereof. This memory cell is well known as a one-transistor one-capacitor type memory cell. Such memory cells are widely used for large capacity DRAMs because of its simple structure contributing to the improvement in integration of the memory cell array.
According to the large storage capacity of DRAMs, high integration is required in memory cell array 51. Row decoder 53 adjacent to memory cell array 51, sense refresh amplifier 55, and column decoder 54 of the peripheral circuit are formed to comply with the dimension of memory cell array 51. Therefore, larger scale integration is required in the above mentioned row decoder 53 and the like according to the increased scale of integration of memory cell array 51. Great increase in integration density is not required for row-and-column address buffer 52 of the peripheral circuit which is not adjacent to memory cell array 51, even if memory cell array 51 is increased in integration density.
FIG. 4 is a sectional view showing a contact structure of a row decoder forming a peripheral circuit of a conventional DRAM. Referring to FIG. 4, a row decoder 53 forming a peripheral circuit of a DRAM comprises a semiconductor substrate 1; element isolation regions 2a and 2b for isolating elements formed on semiconductor substrate 1; impurity implanted layers 5a, 7a and 5b, 7b formed in the region enclosed by element isolation regions 2a and 2b with a predetermined distance therebetween; gate electrodes 3a and 3c formed directly on element isolation regions 2a and 2b, respectively; a gate electrode 3b formed between impurity implanted layers 5a, 7a and 5b and 7b with a gate insulating film 14 thereunder; sidewalls 6a, 6b, and 6c formed at the sidewalls of gate electrodes 3a, 3b and 3c; insulating films 4a, 4b and 4c formed over gate electrodes 3a, 3b and 3c, respectively; a polysilicon pad 8a of electrode material connected to impurity implanted layers 5a and 7a, and formed at the sides of and over gate electrodes 3a and 3b with sidewalls 6a and 6b and insulating films 4a and 4b therebetween; a polysilicon pad 8b connected to impurity implanted layers 5b and 7b, and formed at the sidewalls of and over gate electrodes 3b and 3c with sidewalls 6b and 6c and insulating films 4b and 4c therebetween; an interlayer insulating film 12 formed all over semiconductor substrate 1 with contact holes 15a and 15b formed above polysilicon pads 8a and 8b, respectively; an upper layer wiring 13a formed on interlayer insulating film 12 and within contact hole 15a to contact polysilicon pad 8a; and an upper layer wiring 13b formed on interlayer insulating film 12 and within contact hole 15b to contact polysilicon pad 8b.
Row decoder 53 implementing the peripheral circuit of a conventional DRAM is provided with polysilicon pads 8a and 8b between upper layer wirings 13a and 13b and impurity implanted layers 5a, 7a, and 5b, 7b, respectively. The formation of polysilicon pads 8a and 8b simplifies the process of forming upper layer wirings 13a and 13b to solve difficulties encountered in the manufacturing process.
If polysilicon pads 8a and 8b are not provided, it is necessary to contact upper layer wirings 13a and 13b directly to impurity implanted layers 7a and 7b, respectively. The surface area of the connecting region between impurity implanted layers 7a and 7b and upper layer wirings 13a and 13b are reduced in accordance with the scale of element integration increased. The magnitude of contact holes 15a and 15b that can be formed in interlayer insulating film 12 is limited due to manufacturing techniques. It is difficult to form contact holes 15a and 15b smaller than a certain dimension. If the area of the above-mentioned connecting region becomes smaller than the most minimum contact holes 15a and 15b allowable under the manufacturing technology, it is difficult to form contact holes 15a and 15b through to the surface of the connecting regions. This also results in difficulty in forming upper layer wirings 13a and 13b. This problem is overcome by forming polysilicon pads 8a and 8b between upper layer wirings 13a and 13b and impurity implanted layers 7a and 7b, respectively, to assist the formation of contact holes 15a and 15b above polysilicon pads 8a and 8b, whereby upper layer wirings 13a and 13b can be formed with ease. Polysilicon pads 8a and 8b are indispensable where elements are highly integrated to reduce the surface area of the connecting region between upper layer wirings 13a and 13b and impurity implanted layers 7a and 7b.
FIGS. 5A-5F are sectional views of the structure of the row decoder of the DRAM of FIG. 4 for explaining the manufacturing process.
Referring to FIG. 5A, element isolation regions 2a and 2b are selectively formed on semiconductor substrate 1. Referring to FIG. 5B, gate insulating film 14 is formed by thermal oxidation. An electrode material 3 such as of polysilicon doped with impurities is deposited on gate insulating film 14. Insulating film 4 such as of silicon oxide film is deposited over electrode material 3. Electrode material 3 and insulating film 4 are removed by photolithography and etching, leaving only the portion where gate electrodes 3a, 3b and 3c are formed. Ions having a conductivity type opposite to that of semiconductor substrate 1 are implanted into semiconductor substrate 1 to form impurity implanted layers 5a and 5b. Referring to FIG. 5d, an insulating film (not shown) such as of silicon oxide film is deposited all over semiconductor substrate 1 and etched back to form sidewalls 6a, 6b and 6c. Then, ions of a conductivity type opposite to that of semiconductor substrate 1 are implanted between the adjacent gate electrodes on semiconductor substrate 1 to form impurity implanted layers 7a and 7b. Referring to FIG. 5E, a material 8 having conductivity is formed over impurity implanted layers 5a, 7a and 5b, 7b. Referring to FIG. 5F, polysilicon pads 8a and 8b are formed by patterning material 8 having conductivity. Interlayer insulating film 12 is deposited all over the surface, and contact holes 15a and 15b are formed. Lastly, upper layer wirings 13a and 13b are formed above interlayer insulating film 12 and within contact holes 15a and 15b, as shown in FIG. 4.
As mentioned in the foregoing, the row decoder forming the peripheral circuit of a conventional DRAM is provided with polysilicon pads 8a and 8b between upper layer wirings 13a and 13b and impurity implanted layers 5a, 7a, and 5b, 7b to ease the formation of upper layer wirings 13a and 13b. High integration is required for row decoders according to the scale of integration increased in DRAMs. Therefore, elements implementing a row decoder are miniaturized to shorten the length of the gate electrode itself and the distance between adjacent gate electrodes. This causes an inconvenience that the conventional manner of photolithographing and etching polysilicon pads 8a and 8b above gate electrode 3b becomes difficult to carry out. The miniaturization of elements led to a problem that polysilicon pads can be formed only with difficulty. Even if polysilicon pads could be formed in cases where elements are miniaturized, it was difficult to accurately form the upper layer wirings on the polysilicon pads, resulting in the following inconvenience. That is to say, there was possibility of the upper layer wiring and the gate electrode being short-circuited due to one portion of the upper layer wiring formed directly on the gate electrode. There was also an inconvenience that it was necessary to reduce the contact inside diameter of the contact hole when silicon pads can not be formed. This resulted in difficulty in performing photolithography and etching for forming contact holes.
In conventional DRAMs, it was difficult to form a polysilicon pad as a conductive layer between a wiring layer and an impurity region, whereby contacts could not be formed with ease when elements are miniaturized according to larger scale integration of semiconductor device with reduced distance between adjacent gate electrodes.